In fabrication of semiconductor devices, bitcell arrays may be separated by strap and edge cells. However, reducing a resulting size of strap and edge cells is restricted due to process limitations, particularly for 20 nm technology nodes and beyond. In some cases, strap and edge cells have increased in size when utilizing 20 nm technology compared to previous technologies.
A need therefore exists for methodology enabling a reduction in edge and strap cell size for a design, and the resulting device.